Tailored for AI High-Performance Computing, TSMC's 1.6nm-class A16 Process Targets Mass Production in Q4

TSMC's advanced process technology has achieved another key milestone.

Recently, citing industry sources, Taiwan media outlet DigiTimes reported that TSMC has completed the development and verification of its A16 process and plans to enter mass production in the fourth quarter of this year. As TSMC's first angstrom-class CMOS platform adopting the "Super Power Rail" backside power delivery architecture, A16 targets applications with extremely high demands for computing power, energy efficiency, and power stability, such as AI and High-Performance Computing.

It is reported that compared to the previous-generation N2P process, A16 can achieve an 8% to 10% performance improvement at the same power consumption, or reduce power consumption by 15% to 20% at the same performance level, while increasing transistor density by 8% to 10%. Its core advantage lies not only in the introduction of backside power delivery but also in minimizing changes to front-side transistor structures and the existing design ecosystem.

Backside Power Delivery Breaks the "Routing Bottleneck" in Advanced Processes

As process nodes continue to shrink, the front side of traditional chips must handle both power delivery and signal interconnection. The limited routing space is increasingly unable to meet the needs of High-Performance Computing chips, exacerbating issues such as line congestion and IR drop (resistive voltage drop).

The concept of backside power delivery involves migrating the power network from the front to the back of the chip, thereby freeing up front-side routing space for signal interconnections and reducing resistance and voltage drop in the power delivery path. However, this technology is not simply a matter of "moving the power to the back." Backside power delivery typically requires adjustments to transistors, standard cells, and even the entire design flow, potentially imposing high IP restructuring and design migration costs on customers.

TSMC's A16 utilizes dedicated vertical backside contacts (VB) to connect power directly to the source and drain of transistors, separating the power delivery network from the signal network.

More importantly, TSMC aims to keep changes to the front-side structure to a minimum. It is reported that A16 retains the gate density and NanoFlex design flexibility of N2P, maintaining compatibility with the existing chip design ecosystem as much as possible while improving power efficiency.

This means that for customers who have already designed based on TSMC's advanced processes, migrating to A16 may not require large-scale restructuring of standard cells and design architecture. This advantage is particularly important for AI accelerators and High-Performance Computing chips, which have long design cycles and high IP complexity.

AI Computing Demand Drives Accelerated Evolution of Advanced Processes

The launch of A16 is driven by the higher requirements that AI chips place on advanced processes.

AI accelerators and High-Performance Computing chips typically integrate a large number of computing units, with far higher demands for power integrity, signal routing, and energy efficiency than traditional chips. Backside power delivery can free up front-side routing resources and improve power efficiency, making it regarded as an important technical path for further enhancing the performance and energy efficiency of AI chips.

If A16 enters mass production in the fourth quarter of this year as planned, TSMC will be the first to accumulate large-scale production experience with backside power delivery. As demand for AI computing power continues to grow, whether A16 can win customer favor through its combination of performance, energy efficiency, and design compatibility will become an important point of observation for TSMC's competitiveness in the next stage of advanced process technology.