Cadence expands cooperation with Taiwan Semiconductor to accelerate AI advanced process chip development
Cadence recently announced an expansion of its collaboration with Taiwan Semiconductor to support AI chip designs for advanced processes such as N3, N2, A16, and A14. This collaboration will provide a complete set of intellectual property and design infrastructure, significantly reducing the number of design iterations and shortening the mass production cycle. Cadence also launched AI super agents ViraStack and InnoStack, and partnered with Google Cloud to enhance computational support for design verification. Both parties will also jointly promote design innovations in multi-chip stacking and advanced packaging
According to Zhitong Finance APP, global electronic design automation (EDA) leader Cadence (CDNS.US) recently announced an expansion of its strategic cooperation with foundry giant Taiwan Semiconductor (TSM.US), extending support for artificial intelligence chip design to TSMC's advanced processes N3, N2, A16, and A14. Key players in the chip ecosystem, such as NVIDIA (NVDA.US) and Arm (ARM.US), have also expressed support, accelerating the industrial collaboration around advanced processes and AI-driven design.
According to information disclosed by Cadence, this expanded cooperation will provide a full set of intellectual property (IP), end-to-end design infrastructure that can be directly approved, and advanced certification processes required for AI chip design at TSMC's aforementioned advanced technology nodes. Cadence stated that this will significantly reduce the number of iterations in chip design and shorten the cycle from design to mass production.
On the technical level, Cadence has deeply integrated agentic artificial intelligence (Agentic AI) into the chip design process. At the recent CadenceLIVE 2026 conference, the company launched two AI super agents—ViraStack and InnoStack—supporting end-to-end automated design from chip specification formulation to physical sign-off. Early customer feedback indicates that design production efficiency has improved by 3 to 10 times. Meanwhile, Cadence has partnered with Google Cloud to deploy the ChipStack AI super agent on the cloud platform, providing scalable computing power support for large-scale design verification.
In the field of analog design, Cadence has embedded agentic AI into its Virtuoso Studio design environment, supporting the migration of analog circuit design from TSMC's N2 to A14. Additionally, 3D-IC and chiplet technology are also key focus areas of the collaboration, with both parties jointly promoting innovation in the design processes of multi-chip stacking and advanced packaging.
Tim Costa, Vice President and General Manager of NVIDIA's Computing Engineering, noted in response to the collaboration: "The growing scale and complexity of next-generation AI chips require us to integrate accelerated computing and agentic AI into every aspect of the chip design cycle. Through collaboration with Cadence, NVIDIA is helping its design teams and the global semiconductor ecosystem optimize performance and accelerate the delivery of the world's most advanced AI architectures."
Eddie Ramirez, Vice President of Marketing for Arm's Cloud AI business unit, also stated: "Ecosystem collaboration among design and manufacturing partners, including Cadence and TSMC, is crucial for driving the next generation of AI and high-performance computing (HPC) deployment infrastructure based on Arm architecture."
It is worth noting that Cadence is not the only EDA supplier deepening collaboration with TSMC. During the same industry window, Synposys and Siemens EDA also announced expansions of their cooperation with TSMC in the advanced process field, covering 3nm to A14 technology nodes. TSMC's certification mechanism through the EDA alliance is increasingly evident in building an advanced process design ecosystem with the three major EDA vendors According to estimates from industry research institutions, the global EDA market is expected to reach USD 20.78 billion by 2026, with the AI EDA segment projected to grow from USD 4.27 billion in 2026 to USD 15.85 billion by 2032, achieving a compound annual growth rate of 24.4%, far exceeding the growth rate of the traditional EDA market.
This upgrade in cooperation reflects two key trends in the AI chip competition. First, in the context of scarce production capacity, "design efficiency" has become the core asset for differentiated competition. TSMC's 3nm capacity is currently fully loaded, prioritizing supply to leading cloud AI and ASIC manufacturers such as NVIDIA, AMD, and Broadcom; the 2nm capacity has been completely booked by global tech giants like Google, AWS, and Qualcomm. In this context, the ability to use efficient EDA tools to shorten design iteration cycles and enter mass production ahead of competitors will directly impact the market positioning of chip manufacturers.
Second, the competition for advanced processes has moved into the Angstrom era. TSMC's A16 process is expected to enter mass production in 2027, while the A14 process is further advancing towards the Angstrom level. The early certification of EDA tools means that chip design companies can start design work 12 to 18 months before the process officially enters mass production, which is crucial for seizing the market time window for AI chips.
Analysts point out that in the increasingly heated arms race for AI computing power, EDA tools and advanced process segments at the upstream of the industry chain are demonstrating stronger performance certainty and bargaining power. The news of Cadence expanding its cooperation with TSMC may just be the beginning of this value reassessment process
