Analysis of TSMC's Top Ten Investor Questions: AI Demand, Capacity Expansion, and Competitive Landscape

With Tesla's announcement of its TeraFab self-built chip factory plan as the latest landmark event, coupled with concerns over liquefied natural gas supply triggered by Middle East tensions and the gradual catching up of manufacturing technology by Intel and Samsung, the competitive and supply chain environment surrounding TSMC is becoming more complex.

According to the "Chasing Wind Trading Desk," JPMorgan, in its latest research report on March 24th, systematically addressed the top ten investor concerns, covering dimensions such as capital expenditure trajectory, capacity planning, competitive landscape, packaging strategy, and supply chain risks, providing a relatively comprehensive fundamental assessment framework for the market.

JPMorgan maintained its "overweight" rating on TSMC with a target price of NT$2,250. The firm expects TSMC's USD revenue to achieve over 30% growth in 2026, driven by strong demand for N3, accelerated ramp-up of N2 capacity, expansion of advanced packaging business, and a significant increase in blended average selling price.

In its latest AI revenue growth forecast, TSMC has raised its Compound Annual Growth Rate (CAGR) guidance for AI revenue from 2024 to 2029 from the mid-40% range to the mid-to-high 50% range. Concurrently, JPMorgan projects capital expenditure to potentially exceed $60 billion in 2027 and approach $70 billion in 2028.

Capital Expenditure Surges, Capacity Ramp-up Cycle Lengthens

JPMorgan believes TSMC's capital expenditure is entering a new upward inflection point. The guided range of $52 billion to $56 billion for 2026 represents a substantial increase from previous years, and the company has explicitly stated that its capital expenditure for the next three years will be "significantly higher" than the past three years. According to the firm's estimates, capacity growth will re-accelerate from the previous 4%-5% to the high single digits or approximately 10% level.

The expansion pipeline spans multiple nodes and geographies:

N3 node covers Fab 18 P9 in Tainan, Taiwan, P2 in Arizona, and P2 in Japan;

N2 node is primarily located in Kaohsiung P1 to P5, and potentially Fab 18 P10 to P12 in Tainan, Taiwan;

A14/A10 nodes correspond to Kaohsiung P6 to P8 and the Taichung plant in Taiwan;

TSMC is also planning a new Phase 8 campus in Tainan, Taiwan, dedicated to A10 and future process nodes.

It is worth noting that the cycle between capital expenditure and actual capacity release is lengthening. JPMorgan points out that the current expenditures for the most advanced nodes may not translate into effective capacity until 2028 at the earliest – this is because N2 produces fewer wafers per unit cleanroom area than N3 and has a longer construction period.

Competitive Moat Continues to Widen, Market Share Erosion Risk Limited

Regarding market concerns about TSMC ceding market share due to a conservative expansion pace, JPMorgan's assessment is: overall market share risk is limited.

The firm analyzes that chip design cycles require at least two to three years, and achieving mass production ramp-up at a specific foundry takes another one to two years, resulting in a total switching cycle of three to five years with extremely high switching costs.

From a technological competitiveness perspective, the firm estimates that Intel's 18A currently offers performance comparable to TSMC's N3E, while Samsung's 2nm roughly matches TSMC's 3nm, remaining about a generation behind. TSMC's N2 is already in mass production, whereas Intel's 14A PDK v1.0 is expected to be available earliest by the end of 2026. TSMC maintains a lead of approximately two years in advanced process technology.

JPMorgan acknowledges that due to persistent tight advanced process capacity, collaborations between Samsung and Tesla, and Intel and CSPs will continue to draw market attention, but believes the impact of these dynamics on TSMC's actual market share is likely to be limited.

Packaging Strategy Shifts, Outsourcing Proportion Increases

In terms of advanced packaging positioning, JPMorgan believes TSMC views it as an "enabler" to drive front-end wafer sales, rather than an independent profit growth driver. This positioning will allow TSMC to be more flexible in its outsourcing strategy.

Specifically, the On-Substrate (oS) process within CoWoS is expected to be fully outsourced to ASE, and CoW orders are gradually migrating to Outsourced Semiconductor Assembly and Test (OSAT) providers. JPMorgan also points out that advanced packaging does not constitute a stepping stone for competitors like Intel to enter the front-end foundry business.

Looking ahead, TSMC's strategic focus is expected to shift towards CoPoS and 3D-SoIC. With Nvidia potentially introducing 3D stacking in its Feynman architecture, and multiple ASIC customers migrating to N2-based 3D-SoIC, the expansion of 3D-SoIC is anticipated to be the focus of the next phase.

Constrained by land and cleanroom resources, the prioritization between advanced packaging and advanced process nodes will tilt towards the latter, further increasing the OSAT outsourcing proportion in the next two to three years.

What is the Impact of Tesla's TeraFab?

Elon Musk recently announced the TeraFab plan, aiming to establish a domestic AI chip production system in the United States with an annual capacity of 1 terawatt, covering logic, memory, and advanced packaging. JPMorgan believes that the probability of TeraFab posing a substantial impact on TSMC is currently low.

The firm outlines three major obstacles:

First, advanced process technology is highly concentrated; currently, only TSMC, Intel, and Samsung possess production-validated advanced processes, while IBM only offers laboratory-level process roadmaps;

Second, moving from process to mass production requires extensive engineering accumulation, involving supply chains for equipment, EDA, materials, and chemicals, with yield costs at each step of hundreds of manufacturing processes;

Third, an N2 wafer fab with a capacity of 100,000 wafers per month would cost $50 billion to $60 billion at current prices, and continuous R&D investment is required to maintain generational technological leadership across processes.

JPMorgan points out that technological innovations in the semiconductor field (such as FinFET, Gate-All-Around, EUV, etc.) typically take 15 to 20 years from laboratory to mass production. Whether this cycle can be significantly compressed is a key variable. Although Musk has a track record of excellent execution, the firm believes that disrupting the status quo may require genuine breakthroughs at the physical layer.

Capacity Node Planning and EUV Procurement

Regarding specific capacity figures, JPMorgan estimates that N3 capacity will reach 165,000 to 170,000 wafers per month by year-end, higher than the previous benchmark forecast of approximately 150,000 wafers per month. This is mainly due to the utilization of Fab 15's N7 and 28nm capacity for cross-fab operations and the early introduction of Fab 18 P9.

Looking ahead to 2028, with the full ramp-up of Fab 18 P9, the start of mass production at Arizona P2 in the second half of 2027, coupled with Japan P2 and new campus facilities (Fab 18 P10 to P12), total N3 capacity is expected to exceed 200,000 wafers per month.

For N2, capacity is projected to reach approximately 100,000 wafers per month by the end of 2026, with potential expansion to 200,000 to 240,000 wafers per month over the next three years. Kaohsiung P1 to P5 and Arizona P3 will be the primary sources of incremental capacity.

In terms of EUV equipment procurement, JPMorgan anticipates that TSMC will purchase 29 to 31 units in 2026, an increase from 21 to 23 units in 2025. Critically, High-NA EUV will not be used for N2, A16, or A14 nodes, and is expected to be introduced earliest with the A10 process node (around 2030-2031).

Gross Margin Outlook and Supply Chain Risks

JPMorgan forecasts that TSMC's gross margin in the first half of 2026 could reach the high 60% to 70% range, benefiting from strong demand for advanced processes, an increased proportion of urgent orders (hot-run and super hot-run), favorable TWD exchange rates, and the continued conversion of idle N7 and 28nm capacity for advanced process use. Depreciation expense growth is also expected to be lower than revenue growth (19% in 2026 compared to over 30% revenue growth).

On the risk front, approximately 48% of power generation in Taiwan relies on liquefied natural gas (LNG), with about 33% of LNG imports coming from Qatar and local storage capacity sufficient for only about 11 to 15 days.

Disruptions in the Middle East could lead to rising energy costs, posing the primary pressure on gross margins in the second half of 2026, with peak risk concentrated in the August-September summer electricity consumption season. JPMorgan believes that given the strategic importance of the semiconductor industry, the probability of actual production interruptions is low, and Taiwan is expected to prioritize power supply for industrial use.

Regarding shortages of specialty gases like helium, JPMorgan's research indicates that TSMC currently has over a month's inventory and is actively sourcing from alternative channels (at a cost premium of 2 to 4 times), while also increasing gas recycling efficiency. It is expected that the shortage pressure can be safely navigated.

Blended Average Selling Price Expected to Continue Rising

On the pricing front, JPMorgan believes that recent market rumors of price increases are merely a reiteration of the agreed-upon 6% to 10% price hike for leading-edge processes in 2026 (negotiated in Q3 2025, effective from January 2026), and do not represent a new round of comprehensive price increases.

However, the blended average selling price is still continuously increasing – the rising proportion of urgent orders (with premiums of 50%/100%), HPC customers becoming the main demand drivers for N3, and more customers opting for multi-year price contracts are collectively expected to drive an approximately 20% increase in TSMC's blended average price in 2026.

Regarding Co-Packaged Optics (CPO), JPMorgan believes that CPO's direct contribution to TSMC's revenue will be quite limited, as the cost of related building blocks is significantly lower than the average price of advanced process wafers (HPC N3 wafers cost approximately $26,000 to $30,000). OSAT partners and the testing ecosystem will be larger beneficiaries of CPO ramp-up.

Based on a 12-month forward P/E ratio of approximately 20 times, JPMorgan has set TSMC's target price for December 2026 at NT$2,250, which is higher than the stock's five-year historical average valuation multiple, reflecting the firm's positive assessment of the sustained driving force of AI fundamentals.