Samsung accelerates the design of customized HBM4E, expected to be completed by mid-2026, with SK Hynix and Micron following suit

As the competition in high bandwidth memory (HBM) technology heats up, storage chip giants are accelerating their layout in the customized HBM4E field. Samsung Electronics has significantly increased its R&D investment and is expected to complete the design work for its customized HBM4E by mid-2026, marking a shift in next-generation storage technology from standardized products to high-performance customized solutions that meet specific customer needs.

According to The Elec, Samsung Electronics' customized HBM4E design plan is set to be completed between May and June 2026. This timeline indicates that while HBM4 still primarily consists of standardized products, the industry's focus is rapidly shifting towards customized HBM4E and future HBM5. Meanwhile, competitors SK Hynix and Micron are also advancing similar timelines, with major memory manufacturers not showing significant gaps in the R&D progress of next-generation technologies.

To meet the growing demand for customization, Samsung has adopted an aggressive strategy, establishing dedicated HBM teams for both standardized and customized designs, and recently hiring 250 engineers specifically for customized projects, targeting tech giants such as Google, Meta, and Nvidia. The industry widely expects HBM4E to officially hit the market in 2027, while HBM5 is anticipated to debut in 2029.

This strategic shift not only reflects the surge in demand for differentiated hardware in the high-performance computing market but will also reshape the collaboration model between storage manufacturers and foundries. As the logical functions of basic bare chips become increasingly complex, the introduction of advanced process technologies becomes crucial, with major manufacturers attempting to secure advantageous positions in the future AI computing power competition through different technological paths and partnerships.

Samsung's Full Commitment to Customized HBM

Samsung Electronics is accelerating its R&D process for HBM4E. According to The Elec, the company has entered the backend design phase of the basic bare chip. The overall design cycle for HBM typically lasts about 10 months, with the backend design phase accounting for approximately 60% to 70% of the entire timeline. This phase mainly involves physical design, which occurs after the frontend register transfer level (RTL) logic development is completed, focusing on the layout and connection of circuits. Once this phase is completed, the final design data will be sent to the foundry for tape-out production.

The basic bare chip plays a core role in the HBM architecture, responsible for controlling the data read and write operations of stacked DRAM and error correction, directly determining overall performance and stability. As a result, customers are increasingly demanding the integration of additional logical functions into the basic bare chip, driving the demand for customized HBM.

In terms of process technology, Samsung is seeking a greater technological leap. According to ZDNet, the HBM4 logic bare chip that Samsung commercialized this year uses a 4nm process, while for customized HBM, the company plans to further adopt a 2nm node to achieve higher performance breakthroughs.

SK Hynix and Micron Rely on TSMC Ecosystem

While Samsung is advancing its self-developed solutions, SK Hynix and Micron are responding to customization challenges by deepening their collaboration with TSMC. The Elec cites industry insiders stating that SK Hynix and Micron are expected to complete their respective customized HBM4E developments around the same time as Samsung, with the three major manufacturers currently having similar R&D progress According to ZDNet, SK Hynix is closely collaborating with TSMC to develop the next generation of HBM basic bare chips and other advanced products, and is working with SanDisk to promote the international standardization of high bandwidth flash (HBF). In terms of process selection, the Korea Financial Times pointed out that SK Hynix will use TSMC's 12nm process for mainstream server basic bare chips, while upgrading to a 3nm process for high-end designs such as NVIDIA's flagship GPUs and Google's TPUs.

As for Micron, according to a previous report by Tom’s Hardware, the company has commissioned TSMC to manufacture its HBM4E basic logic bare chips, aiming for production by 2027. However, the media noted that Micron insists on using existing DRAM processes to control costs, which is seen as a structural disadvantage in the custom HBM race. Although Micron has begun exploring TSMC's processes for HBM4E, industry observers generally believe that its pace in this field may lag behind Samsung and SK Hynix