Behind the Rise of Taiwan Semiconductor's CoWoS: Once Sat on the Bench for 10 Years

Artificial Intelligence (AI) drives Taiwan Semiconductor's advanced packaging CoWoS to great success. Contrasting with over a decade ago when the technology was just developed, it was a different story as it was virtually unknown. Insiders familiar with the situation revealed that back then, Taiwan Semiconductor's CoWoS had no customers, with only Xilinx willing to adopt it, but only ordering 50 pieces per month, a pitifully small quantity. This is in stark contrast to the current scenario where demand for production capacity is soaring.

In October 2013, Taiwan Semiconductor issued a press release stating that Xilinx successfully mass-produced 28-nanometer products using CoWoS technology, confirming the claims made by industry insiders. At that time, Taiwan Semiconductor pointed out that Xilinx used the company's CoWoS (Chip-on-Wafer-on-Substrate) technology to develop 28-nanometer 3D IC products, integrating multiple chips onto a single system to significantly reduce size and enhance power consumption and efficiency.

Insiders mentioned that over a decade ago, when Taiwan Semiconductor developed the CoWoS technology, there were no customers except for Xilinx, which ordered only 50 pieces per month, an extremely small quantity. It can be said that the quantity was pitifully small. At that time, Taiwan Semiconductor's founder, Morris Chang, heeded the advice of the chief R&D officer, Shang-Yi Chiang, to venture into advanced packaging. He allocated a large team of 400 engineers and $100 million in R&D resources. However, the development of the CoWoS technology did not bring any business. Shang-Yi Chiang mentioned in an interview last year that this became a joke within the company, putting him in a very awkward position.

Shang-Yi Chiang shared that he had promoted the CoWoS technology to customers everywhere, but no one was willing to use it. Later, during a dinner with a vice president of a customer, the reason for not adopting CoWoS was casually mentioned as the high price. If selling at 7 cents per square millimeter was too expensive, they would only consider using it if it was sold at 1 cent per square millimeter. This realization prompted him to immediately instruct the R&D manager to develop a cost-reducing technology, which turned out to be another advanced packaging technology called InFO.

InFO is an advanced packaging technology adopted by customers such as Apple for smartphone chips, and it has become a major success for Taiwan Semiconductor. It is rumored in the industry that InFO has contributed approximately over $3 billion to Taiwan Semiconductor's revenue in a year.

Initially, Taiwan Semiconductor's CoWoS production capacity was limited. However, in recent years, the development of AI has outpaced expectations. AI chips adopting CoWoS advanced packaging have led to a sudden surge in demand, causing Taiwan Semiconductor to urgently expand production. The company's production capacity is expected to double for both this year and next year, with the balance of supply and demand projected to be achieved by 2026. Taiwan Semiconductor stated that it will continue to collaborate with professional back-end testing and packaging factories to meet customer demands. At the investor conference held on the 18th, the leading wafer foundry Taiwan Semiconductor announced that it will increase the production capacity of CoWoS advanced packaging, with next year's estimate exceeding a doubling rate.

Wei Zhejia revealed that this year, the CoWoS production capacity is expected to double and increase further beyond initial expectations. The related production capacity increase by 2025 is also projected to exceed a doubling rate, as Taiwan Semiconductor continues to collaborate with professional back-end testing and packaging factories (OSAT) to expand advanced packaging capabilities in response to strong customer demand When asked about when supply and demand can be balanced, Wei Zhejia stated that the current supply of advanced CoWoS packaging remains tight, hoping that the tight situation can gradually ease by 2025, and supply and demand can reach a balance by 2026.

TSMC previously expected that the compound annual growth rate of CoWoS capacity from 2022 to 2026 would exceed 60%.

TSMC's advanced packaging and testing plant 5 in Zhongke is under construction and is expected to mass produce CoWoS by 2025; the advanced packaging and testing plant 6 in Miaoli Zhunan, which integrates SoIC, InFO, CoWoS, and advanced testing, will be put into operation in early June 2023.

TSMC's advanced packaging and testing plant 7 in Chiayi started construction in May this year. Originally planned to mass produce SoIC and CoWoS by 2026, construction was temporarily halted in June when suspected relics were discovered locally.

What is TSMC's CoWoS?

CoWoS (Chip-on-Wafer-on-Substrate) is a 2.5D, 3D packaging technology that can be divided into "CoW" and "WoS".

CoW (Chip-on-Wafer) refers to stacking chips, while WoS (Wafer-on-Substrate) refers to stacking chips on a substrate.

Therefore, CoWoS means stacking chips and packaging them on a substrate. Depending on the arrangement, it can be divided into 2.5D and 3D. The advantage of this packaging technology is to reduce chip space, as well as reduce power consumption and costs.

The main difference between 2.5D and 3D packaging technologies lies in the stacking method.

The most well-known 2.5D packaging is TSMC's CoWoS, which conceptually uses a horizontal stacking method to place semiconductor chips on an intermediate layer or connect chips through silicon bridges. Finally, through the packaging process, they are connected to the underlying substrate, allowing multiple chips to be packaged together, achieving a smaller package size, lower power consumption, and fewer pins. Essentially, it is still horizontal packaging, just making the distance between chips closer.

3D packaging uses a three-dimensional packaging structure to cross-package multiple chips on the same or different layers within the same chip. Through the use of Through Silicon Vias (TSV) to connect electronic signals between different chips above and below, signal delay is reduced. It is true vertical packaging, but currently, the technology of TSV is not yet mature in terms of design, mass production, and supply chain. Based on cost considerations, the industry currently mostly adopts 2.5D packaging Author: Semiconductor Industry Observer, Source: Semiconductor Industry Observer, Original Title: "Behind the Success of Taiwan Semiconductor's CoWoS: Endured 10 Years of Sitting on the Bench"