Taiwan Semiconductor 2024Q2: Wafer fabrication 2.0 drives market doubling
TSMC defines wafer foundry 2.0, including packaging, testing, mask manufacturing, and other IDM (excluding storage). Under the new definition, the market size has increased from $115 billion to $250 billion
Author: Zhang Yifan
Editor: Shen Siqi
Source: Hard AI
Following ASML's release of better-than-expected revenue and profit for 2024Q2, Taiwan Semiconductor also announced its performance for 2024Q2. The financial report shows that revenue, net profit, operating profit margin, and gross profit margin all exceeded the company's guidance and Bloomberg's expectations, once again demonstrating the strong demand for AI.
During the conference call, Taiwan Semiconductor also revealed the latest developments in business expansion, capacity, and processes:
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Raised the 2024 capital expenditure to USD 30 billion to USD 32 billion (previously USD 28 billion to USD 32 billion);
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Defined Wafer Foundry 2.0, expanding the company's business (in addition to wafer foundry, it also includes packaging, testing, mask manufacturing, and all other IDMs except storage). Under the new definition, the company's corresponding market size will double;
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Cowos supply remains tight, and the company maintains its plan for a compound annual growth rate of 60% in capacity over the next few years, stating that Cowos' gross margin is now close to the company's average level (previously lower gross margin);
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Regarding market rumors about price increases for advanced processes, the company did not give a direct response, only mentioning that pricing will be strategic, and emphasizing the target of 53% or higher gross margin;
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In terms of advanced process production plans, the company expects N2 node to start production in 2025, N2P node and A16 node to start production in the second half of 2026;
Regarding guidance, the company stated that in 2024Q3, benefiting from strong demand in AI-related and smartphones, the company's advanced process products will be more favored, and provided Q3 revenue, gross margin, and operating profit margin guidance, each of which exceeded Bloomberg's consensus expectations (see the figure below). The company maintains its forecast of approximately 10% growth in the semiconductor industry (excluding storage) for the full year (under the new definition of Foundry 2.0). The company raised its full-year revenue growth guidance from the lower end of the 20%-30% range to above the middle of the over 20% range.
1. Capital Expenditure
Taiwan Semiconductor has narrowed its 2024 capital budget range to USD 30 billion to USD 32 billion, compared to the previous range of USD 28 billion to USD 32 billion.
The company stated that 70% to 80% of the capital budget will be allocated to advanced process technology, around 10% to 20% will be used for special technologies, and about 10% will be used for advanced packaging, testing, mask manufacturing, and other areas.
2. Wafer Foundry 2.0
Defined Wafer Foundry 2.0 to expand the company's business. In addition to wafer foundry, Foundry 2.0 will also include packaging, testing, mask manufacturing, and all other IDMs (excluding storage) Under the new definition, the market size corresponding to the company doubles. In 2023, the wafer foundry industry is about $115 billion, but under the new definition, it is close to $250 billion. According to the new definition, TSMC's share in the wafer foundry industry is only 28%, and the company expects this share to further increase in 2024.
TSMC predicts that under the new definition, the growth of the wafer foundry industry in 2024 will be close to 10%.
3. Cowos
Currently, Cowos' production capacity is very tight, and the company is continuously increasing capacity to meet customer demand. The company maintains a plan for a compound annual growth rate of 60% for Cowos capacity in the coming years and aims to achieve supply-demand balance by 2025 or 2026. According to the previously disclosed capacity plan, by the end of 2026, TSMC's monthly CoWoS wafer capacity will reach around 60,000 pieces.
In June of this year, Morgan Stanley predicted in a report that with a 60% compound annual growth rate in Cowos capacity, from 2023 to 2026, TSMC's non-wafer revenue compound annual growth rate (CAGR) will reach 31%.
Regarding gross margin, Cowos' gross margin has been significantly lower than the company's average level in the past. However, due to economies of scale and cost improvements, the gross margin has increased significantly in the past two years and is now close to the company's average level.
4. Wafer Foundry Price Increase
Previously, there were rumors in the market that TSMC would raise prices for advanced process products, and Morgan Stanley provided the expected price increase path for various processes in the next 2 years (see the figure below).
During the performance meeting, the company did not give a direct response to the price increase rumors, only mentioning that pricing would be strategic and emphasizing a target of 53% or higher gross margin.
5. N2, N2P, and A16 Node Planning
The company revealed that the N2 node will be mass-produced in 2025, while the N2P and A16 nodes will be mass-produced in the second half of 2026.
In terms of wafer starts, the number of wafer starts in the first two years of N2 will be higher than the first two years of N3 and N5.
In terms of performance, compared to N3E, N2 will increase performance by 10% to 15% at the same power consumption, or reduce power consumption by 25% to 30% at the same performance, with a chip density increase of over 15% compared to N3E. Currently, the development of N2 technology is progressing smoothly, with device performance and yield improvements on schedule or ahead of schedule, and is expected to achieve mass production in 2025. The ramp-up growth curve will be similar to N3. N2P, as an extension of the N2 series, will support smartphone and HPC applications based on N2 and is expected to achieve mass production in 2H26 In terms of the A16 node, Taiwan Semiconductor has adopted the exclusive Super Power Rail (SPR) technology. SPR is an innovative and top-notch power transmission solution, the industry's first solution to use backside contact to maintain gate density and device flexibility. Compared to N2P, A16 offers an 8% to 10% increase in speed at the same power or a 15% to 20% increase in efficiency at the same speed, with a chip density increase of 7% to 10%. A16 is most suitable for specific HPC products with complex signal lines and dense power delivery networks, and is expected to be mass-produced in 2H26.
Taiwan Semiconductor 2024Q2 Performance Analysis
1. Overall Performance in 2024Q2: In 2024Q2, Taiwan Semiconductor's revenue, net profit, operating profit margin, and gross profit margin all exceeded Bloomberg's expectations. In addition, the company has raised its capital expenditure guidance, increasing the 2024 capital expenditure to $30 billion to $32 billion (previously $28 billion to $32 billion). Overall, the quarterly financial report is very impressive.
2. Taiwan Semiconductor 2024Q2 Revenue: Revenue in Q2 2024 was $20.8 billion, exceeding the upper limit of the company's guidance ($19.6 billion to $20.4 billion) and surpassing Bloomberg's consensus estimate ($20.2 billion). The increase in quarterly revenue was mainly due to the growth in shipments of 3nm and 5nm, although the seasonal weakness in smartphones partially offset the growth in advanced processes. Due to strong demand in AI-related and smartphones, the company stated that the demand for N3 and N5 is relatively high in 2024, and raised the full-year revenue guidance to mid-20%+ (previously low-to-mid 20%).
3. Taiwan Semiconductor 2024Q2 Net Profit: Net profit was NT$247.9 billion (up 36% year-on-year, up 10% quarter-on-quarter), exceeding Bloomberg's consensus estimate of $7.22 billion (equivalent to NT$233.2 billion). The better-than-expected net profit was mainly due to higher-than-expected capacity utilization, cost improvements, and more favorable exchange rates, but some profit margins were offset by N3 ramp-up, higher electricity prices in Taiwan, and the cost of transitioning from N5 to N3.
4. TSMC 2024Q2 Gross Margin: The gross margin is 53.2% (a decrease of 0.9 ppts year-on-year, an increase of 0.1 ppts quarter-on-quarter), exceeding the company's previous guidance of about 51%-53%. The main reasons for the growth are mainly due to higher-than-expected capacity utilization, cost improvements, and more favorable exchange rates, but some profit margins are offset by N3 ramp-up, Taiwan electricity price increases, and N5 to N3 conversion costs. In terms of capacity utilization, the company stated at the performance meeting that, benefiting from strong demand for AI and high-end smartphones, the capacity utilization rates for 3nm and 5nm will continue to rise in the second half of 2024.
5. TSMC 2024Q2 Revenue (by process): The revenue distribution by process for the company's 3nm/5nm/7nm processes is 15%/35%/17% (compared to 9%/37%/19% in 24Q1), with advanced processes accounting for a total of 67% (compared to 65% in 24Q1, where 7nm and below are defined as advanced processes). The increase in 3nm revenue share for the quarter was mainly driven by strong demand for AI chips. The company stated that the demand for 3nm is strong, and it does not rule out converting more N5 technology to N3 in the future, as the tool commonality between N5 and N3 exceeds 90% (thus supporting the conversion). TSMC stated that the construction of the N2 factory is progressing smoothly and is expected to achieve mass production in 2025.
6. TSMC 2024Q2 Revenue (by application): The revenue distribution by application for high-performance computing/smartphones/IoT/automotive/consumer electronics/other businesses is 52%, 33%, 6%, 5%, 2%, 2% (compared to 46%, 38%, 6%, 6%, 2%, 2% in the previous quarter), with changes in revenue by application of 28%, -1%, 6%, 5%, 20%, 5% quarter-on-quarter. Among them, the revenue share of high-performance computing exceeds 50% for the first time.
7. TSMC 2024Q2 Revenue (by region): The distribution by region for North America/China/Asia-Pacific/Japan/EMEA is 65%, 16%, 9%, 6%, 4% (compared to 69%, 9%, 12%, 6%, 4% in the previous quarter). It can be seen that North America is still TSMC's largest source of revenue, accounting for 65% of revenue, mainly due to major customers such as Apple, Qualcomm, NVIDIA, AMD, etc. (these are all TSMC's top ten customers and also giants in the AI industry)
8. Silicon Wafer Revenue (USD per wafer): In 2024Q2, silicon wafer revenue reached a historical high of $6662 per wafer, mainly due to the increase in the proportion of revenue from 3nm technology.