AI Chip Roadmap: 3 charts and 7 major impacts

Author: Li Xiaoyin

Source: Hard AI

In the overnight US stock market, semiconductor giant Taiwan Semiconductor's market value surpassed $1 trillion during trading, and Taiwan's stock price also hit a historic high on Monday, indicating a strong demand in the market for high-end chips, especially AI chips.

On July 8th, analysts Mark Li and Stacy A. Rasgon from the investment bank Bernstein released a research report summarizing the AI chip technology roadmap until 2027. They analyzed the design architecture, wafer nodes, HBM, and advanced packaging, discussing the potential impacts.

AI Chip Iteration Accelerates, NVIDIA May Become the Biggest Winner

Bernstein believes that AI chips will accelerate in development, especially as NVIDIA has increased its iteration speed to "one update per year."

The technology roadmap shows a leap from Blackwell to Rubin for NVIDIA, including changes in architecture, nodes, HBM, and packaging all within about 1 year—nodes from N4 to N3, HBM from 3E to 4, and packaging size from smaller (a single CoWoS wafer accommodating 16 B100/B200) to larger (a single CoWoS wafer accommodating high single digits to 10 Rubins).

Furthermore, NVIDIA's HBM upgrade from 8hi/192GB to 12hi/288GB will be completed within 6 months.

In comparison, AMD's pace is slightly slower: the MI325X is expected to be released about a year later than the MI300X, and will only upgrade the memory. By 2025, the MI350X will mainly upgrade to the N3 node, but memory and capacity will remain unchanged at HBM3E 288GB.

The report points out that this will bring the first impact: as AI chips iterate faster, NVIDIA's leading advantage over other manufacturers will further expand.

The second impact is the trend of integrating CPU and GPU, memory, and logic. For example, NVIDIA has integrated CPU and GPU in its GB200, helping it leverage its leading position in the GPU field based on Arm CPUs Technical Roadmap Three shows that in order to further promote the development of data transmission, HBM4 may start to provide customer customization services based on basic chip customization. Due to the longer production cycle required for customization of its basic bare die (logic bare die), the integration of logic and storage within HBM may become a major trend.

TSMC's Advanced Packaging Advantage Expected to Continue

The report points out that TSMC's technological advantage will continue from CoWoS-S to CoWoS-L.

It is reported that in CoWoS-S, silicon is used throughout the interposer, while in CoWoS-L, silicon is only used as a "bridge" in areas where dense metal lines pass through, with the rest replaced by mold compounds.

The report predicts that almost all AI chips in the future will be packaged using TSMC's CoWoS, with the next step expected to expand to Microsoft (partially through Marvell) and Meta (through Broadcom). This will also bring the third major impact: as technology advances and customer base expands, TSMC's leading position in the field of advanced packaging is expected to be maintained if not expanded.

Fourth, it is hoped that Samsung can keep up with the pace of HBM3E in a timely manner. Currently, Samsung has not announced the certification of its HBM3E, especially in obtaining certification from NVIDIA.

The report believes that although Samsung started late with HBM3E, the window of opportunity for HBM3E will still provide Samsung with a chance to catch up. NVIDIA is likely to continue using HBM3E in almost all chips in 2025 and chips from other manufacturers in 2026.

Wire Bonding Technology Demand Outlook Optimistic, ASIC Market Expansion

As the transition of nodes continues, the report predicts that AI will make N2 a "super node", but this underestimates the yield and cost burden - as the horizontal expansion increases, advanced packaging awards become increasingly difficult - making wire bonding technology, especially hybrid wire bonding technology, crucial in the field of vertical stacking.

Bernstein holds a structurally optimistic view on the long-term prospects of wire bonding technology. The report believes that the fifth impact is that AI chips and other related applications (wafer-to-wafer, chip-to-wafer, or chip-to-chip) will bring a larger wire bonding technology market.

Sixth, Panel Level Packaging (PLP) is more horizontally expandable than wafer-level packaging, as the former can guarantee better horizontal scalability, but this transformation will require effort and may take longer than expected.

The report suggests that Samsung, with wafers and panels, is trying to create a leading advantage through PLP, which should give it more advantage in this area compared to Intel and TSMC Finally, for ASIC chip providers, the surge in AI chips will attract new entrants and greatly expand the market.

The report indicates that many companies are entering the ASIC (Application-Specific Integrated Circuit) chip field due to the attraction of market growth. ASIC chips have simpler hardware specifications, are more efficient in terms of performance and cost, and are seen as viable alternatives to GPUs. Tech giants such as Amazon, Microsoft, and Meta are developing ASIC chips.

However, since the audience for ASIC chips is mostly internet companies or companies with little experience in the past, they need ASIC service providers to help develop custom chips.

The report points out that Broadcom is currently in a leading position in this field, with revenues reaching billions of dollars and clients including Google, Meta, and others. Additionally, due to its strong technical capabilities in SerDes IP and advanced node packaging, MediaTek also has certain competitiveness