Report: TSMC explores new AI semiconductor packaging technology, allowing more chipsets to be placed on a single wafer

According to Nikkei Asia, Taiwan Semiconductor is exploring a new advanced chip packaging method to meet the increasing demand for computing brought by artificial intelligence.

Insiders revealed that the core of this new method is the use of rectangular substrates measuring 510mm by 515mm, instead of the traditional circular wafers currently used. This design allows for more chipsets to be placed on each substrate, thereby increasing production efficiency. The effective area of rectangular substrates is more than three times larger than circular wafers, with less unused space at the edges.

Although this research is still in the early stages, if the news is true, it will signify a significant technological shift for Taiwan Semiconductor.

Previously, Taiwan Semiconductor considered the use of rectangular substrates to be too challenging. To make this new method successful, Taiwan Semiconductor and its suppliers must invest a significant amount of time and effort in research and development, as well as upgrade or replace numerous production tools and materials.

Taiwan Semiconductor's current advanced chip stacking and assembly technologies, used for producing AI chips for Nvidia, AMD, Amazon, and Google, mainly rely on 12-inch silicon wafers, which are currently the largest available size.

However, with the continuous increase in chip sizes and the demand for more integrated memory, the current industry standard 12-inch wafers may not be sufficient to meet the packaging needs of cutting-edge chips within a few years.

Executives in the chip industry indicate that the size of future packaging will only continue to grow larger to extract more computing power from chips used for AI data center calculations. However, there are still some technical bottlenecks, such as the difficulty of coating photoresist on new-shaped substrates. Driving equipment manufacturers to change their designs requires the support of financially strong chip manufacturers like Taiwan Semiconductor.

Mark Li, a semiconductor analyst at Bernstein Research, believes that overall, this technological transformation may take five to ten years to achieve comprehensive facility upgrades, including the transformation of robotic arms and automated material handling systems.

In addition to Taiwan Semiconductor, Intel and Samsung are also collaborating with suppliers to explore panel-level packaging technology.

With chip packaging and testing service providers such as ASE Technology and display manufacturers such as BOE and Taiwan's Innolux investing resources in developing panel-level chip packaging technology, the semiconductor industry's innovation and diversification process is accelerating