JP Morgan: TSMC's Technological Breakthrough, the Key Engine of the AI Era

On April 24th, TSMC held the 2024 Technology Seminar North America Summit, showcasing many cutting-edge technologies that garnered significant market attention.

In its latest report on the 26th, Morgan Stanley stated that the highlights of this summit include the launch of the A16 process node, the debut of advanced packaging technology SoW, and further innovation in silicon photonics technology. The report emphasized TSMC's leading technological position in the AI era, giving it an "overweight" rating and a target price of NTD 900.

At its North America Technology Seminar, TSMC introduced the A16 process node for the first time, which is its first node to integrate nanosheet transistors and feature backside power delivery using TSMC's Super Power Rail architecture. A16 is expected to enter production in 2026 and is particularly suitable for certain high-performance computing (HPC) applications, especially those benefiting from higher clock speeds. A16 is likely an extension of the N2 family, following the N2 and N2P/N2X. A16 offers significant PPA (performance, power, area) gains and is expected to continue driving demand from fabless customers for the N2 family, especially in the HPC and AI fields.

A14 Process Node and High NA EUV Usage

A14 is an independent new process node outlined in TSMC's annual report, expected to adopt second-generation nanosheet transistors and more advanced backside power delivery networks, bringing comprehensive node PPA advantages. A14 may begin production in 2027-28. As an extension of the N2 family, A16 will not use high NA EUV tools. For A14, TSMC may consider using some high NA EUV tools, but the widespread use is quite limited due to ecosystem readiness (photoresist, mask size scaling, throughput in actual production scenarios).

Next Step in Advanced Packaging Technology: SoW

TSMC also introduced its Wafer-level System (SoW) product for the first time, allowing the packaging of a large number of chips (logic chips, composite SoIC packaging, HBM, and other chips), as well as power and thermal modules at the full 12-inch silicon wafer scale. This represents a significant advancement in advanced packaging complexity and capabilities compared to CoWoS and 3DSoIC, as entire computing systems may be packaged in a single wafer.

Further Innovation in Silicon Photonics Technology

TSMC announced the development of its photon engine (COUPE) to achieve the stacking of photonics and electronic chips, significantly reducing energy consumption and impedance. TSMC expects to lead the development of co-packaged optical technology in 2026. This aligns with TSMC's role as a key partner for Broadcom and NVIDIA (two companies currently leading in advanced co-packaged optical technology).

N2 NanoFlex, N4C, and Advanced Packaging for AutomotiveTSMC has announced the availability of NanoFlex N2, which is an extension of FinFlex announced in N3. This allows customers to mix different types of transistors in the same chip to balance performance, power consumption, and density. TSMC also announced N4C, which will achieve a 9% reduction from N4P, reducing costs for cost-sensitive applications by 2025. Finally, automotive SoCs and ADAS chips are also moving towards advanced packaging, with TSMC starting to provide InFO and CoWoS-R solutions for ADAS chips and SoCs.

Conclusion: TSMC will continue to lead for 3-5 years

Based on the above reasons, Morgan Stanley rates TSMC as "overweight" with a target price of NT$900.

Morgan Stanley's report emphasizes TSMC's leading position in technology innovation and advanced packaging, as well as its critical role in the AI era. Through a series of technological breakthroughs, TSMC is expected to continue to maintain its leading position in the semiconductor industry in the coming years